1. Field of the Invention
This invention relates generally to a semiconductor device and, more particularly, pertains to N+ buried zener structures.
It is well-known in the prior art to use monolithic subsurface or buried zener structures. A typical prior art device has a deep P+ diffusion forming the anode and a shallow N+ diffusion overlapping the deep P+ diffusion to form the cathode. As illustrated, in FIG. 1, a typical prior art buried zener structure includes a P substrate 130, an N- epitaxial layer 10, and N+ buried layer 30 on the boundary between the P- substrate and the N- layer, a P- layer 50 extending from the surface and down into the N- layer, a shallow P+ region 110 within the P- layer 50 and on the surface thereof, a shallow N+ region 70 extending from the surface down and into the P- layer, and finally a deep P+ diffusion region 90 extending from the edge of the N+ region 70 through the P- layer 50 and through the N- layer 10 to the N+ buried layer 30. The negative terminal 170 is attached to the P+ anode region 110 and the positive terminal 190 is connected to the N+ surface cathode region 70. The PN junction of interest (i.e., the subsurface zener metalurgical junction) is formed at 150 beneath the surface and is the intersection of region 70 and region 90. Note that the N+ buried layer 30 is formed as a byproduct in some IC manufacturing techniques and is not required for the efficient operation of this subsurface zener structure.
In some applications, primarily junction isolation (JI) monolithic IC's, the processing step(s) used to create the deep P+ diffusion region 90 may also be used to form the junction isolation diffusion. Consequently, the deep P+ region 90 diffusion of the zener forms a PN junction with the buried N+ layer 30. This is undesirable because the junction formed by the N+ buried layer 30 and the deep P+ diffusion 90 is an unnecessary electrically inactive parasitic junction. In addition, prior art zener structures have other inherent disadvantages because they use a deep P+ channel that is usually of boron which does not diffuse as uniformly as phosphorous and, thus, the junction formed with the shallow N+ region 70 and the deep P+ region 90 is not completely uniform, and therefore the incidence of burst noise is higher. Another disadvantage is that there is a large dynamic resistance and a large parasitic bulk resistance in the voltage sense path between P+ regions 90 and 110 through the P- region 50. This can lead to an undesirable nonlinear relationship between the zener voltage and absolute temperature. Another disadvantage is that the current forced into terminal connection 190 must be withdrawn from terminal connection 170. This leads to a forcing current return path at or near the Si-SiO.sub.2 interface. This, in turn, leads to increased 1/f noise.
The so-called Kelvin subsurface zener structures address the problem of a large parasitic bulk resistance in the voltage sense path by providing two electrical paths, one for the forcing current, and one for the voltage sense (the voltage sense path, theoretically, draws no current). However, Kelvin subsurface zener structures do not address the problem of a large dynamic resistance and the parasitic N+ buried layer/deep P+ diffusion junction. In addition, Kelvin subsurface zener structures are, in some applications, unsatisfactory because they can require a considerable amount of extra area to fabricate them. Further, 1/f noise is proportional to junction area and, therefore, larger structures lead to increased 1/f noise. Lastly, Kelvin subsurface zeners can, at best, approach the noise performance of prior art zeners because of the less uniform diffusion of boron and the fact that the forcing current return path is near the Si-SiO.sub.2 interface.
Thus, there exists a need for an improved subsurface zener structure to be used in monolithic IC's (of which JI monolithic IC's are a subset) that has improved resistance and noise characteristics and can be fabricated as easily as any prior art JI monolithic IC structure.